1. Field
Exemplary embodiments of the present invention relate to a semiconductor designing technology, and more particularly, to a non-volatile memory device, a method for fabricating the non-volatile memory device, and a method for operating the non-volatile memory device.
2. Description of the Related Art
Non-volatile memory devices retain data stored therein although power supply is turned off. Each memory cell of a non-volatile memory device includes a floating gate that is controlled by a control gate and performs a data program operation or a data erase operation by accumulating electrons in the floating gate or discharging the electrons out of the floating gate.
FIG. 1 is a circuit diagram illustrating a conventional non-volatile memory device, and FIG. 2 is a timing diagram describing a method for programming the non-volatile memory device shown in FIG. 1.
Referring to FIG. 1, the conventional non-volatile memory device includes a plurality of strings ST, bit lines BLe and BLo that are coupled with the one ends of the strings ST, respectively, and a source line SL that is coupled with the other ends of the strings ST in common. Each string ST includes a drain selection transistor DST, a plurality of memory cells MC, and a source selection transistor SST that are serially coupled.
The bit lines may include an even bit line BLe and an odd bit line BLo.
Gates of the drain selection transistors DST extend to one another to form a drain selection line DSL, and gates of the source selection transistors SST extend to one another to form a source selection line SSL.
Each of the memory cells MC may include a stacked structure of a floating gate and a control gate. The control gates of memory cells MC extend to one another to form a word line WL.
A program operation, which is an operation of storing a data in a selected memory cell MC, may be performed on a page basis. In particular, an even page program operation for programming a selected memory cell MC, among the memory cells MC of the strings ST coupled with the even bit lines BLe, and an odd page program operation for programming a selected memory cell MC, among the strings ST coupled with the odd bit lines BLo, are performed independently of each other. While an even page program operation is performed, the strings ST coupled with the odd bit lines BLo are kept away from being programmed, and while an odd page program operation is performed, the strings ST coupled with the even bit lines BLe are kept away from being programmed.
Hereinafter, a program operation is described in detail with reference to FIG. 2. For the description purpose, it is described that the strings ST coupled with the even bit lines BLe are programmed while the strings ST coupled with the odd bit lines BLo are not programmed.
Referring to FIG. 2, a ground voltage is applied to the even bit lines BLe as a bit line program voltage, and a voltage of approximately 3.5V is applied to the odd bit lines BLo as a bit line program inhibition voltage (refer to duration {circle around (1)}).
While a bit line program voltage and a bit line program inhibition voltage are applied, a bit line pre-charging is performed (refer to duration {circle around (2)}) by applying a voltage capable of applying both voltages to the strings ST, for example, a voltage of approximately 4V, to the drain selection line DSL.
Subsequently, a selected memory cell MC is programmed (refer to duration {circle around (4)}) by applying a program voltage VPGM and a pass voltage VPASS to a selected word line SEL_WL and the other word lines UNSEL_WL that are not selected.
When the programming of the selected memory cell MC is completed, all word lines WL, the drain selection line DSL, and the bit lines return to the initial states (refer to duration {circle around (5)}).
Before the pass voltage VPASS is applied after the bit line pre-charging is completed, in short, between the duration {circle around (2)} and duration {circle around (4)}, the voltage applied to the drain selection line DSL is decreased to such an extent that the coupling between the odd bit lines BLo and the strings ST may be substantially cut off while maintaining the coupling between the even bit lines BLe and the strings ST. For example, the voltage applied to the drain selection line DSL may be decreased to approximately 2V. This is to prevent an occurrence of a program disturbing phenomenon where the memory cell MC of an odd bit line BLo coupled with the selected word line SEL_WL is programmed by cutting off the coupling between the odd bit lines BLo and the strings ST and boosting the channel voltage of the strings ST coupled with the odd bit lines BLo.
Since the decrease extent of the voltage applied to the drain selection line DSL is to simultaneously satisfy the two conditions of maintaining the coupling between the even bit lines BLe and the strings ST and cutting off the coupling between the odd bit lines BLo and the strings ST, there is little margin. When the voltage applied to the drain selection line DSL is decreased too much, the coupling between the even bit lines BLe and the strings ST is cut off as well and thus the channels of the strings ST coupled with the even bit lines BLe may not maintain the ground voltage. Therefore, the program operation may not be performed properly. Conversely, when voltage applied to the drain selection line DSL is not decreased sufficiently, the coupling between the odd bit lines BLo and the strings ST is maintained and thus program disturbing phenomenon may occur. This is because one even bit line BLe and one odd bit line BLo share one drain selection line DSL.